1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication. More particularly, the present invention relates to a method of fabricating a memory array, such as a memory array of a stack-type DRAM device.
2. Description of the Prior Art
Electronic storage devices such as dynamic random access memory (DRAM) have been an essential resource for the retention of data. Conventional semiconductor DRAM typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor memory often requires densely packed capacitor structures that are easily accessible for electrical interconnection.
The capacitor and transistor structures are generally known as memory cells. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a digit line, one of which addresses a “column” of memory cells while the other addresses a “row” of memory cells.
Recently, there has been increasing research on the buried word line cell array transistor in which a word line is buried in a semiconductor substrate below the top surface of the substrate using a metal as a gate conductor. In such a memory device, the bit line or digit line is often fabricated over the surface of the semiconductor substrate. Therefore, an additional storage node contact or “cell contact” is required for the interconnection between the storage node and the active area of the semiconductor substrate.
However, storage node contact process involves several complicated steps. Furthermore, as integrated circuit designs become denser, it becomes more difficult to isolate a digit line from the adjacent cell contact in the array. Thus, shorting between cell contact and digit line or between cell contact and cell contact may occur.